Phase change memory (PCM) devices store data using phase change materials, such as Chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance and the crystalline phase exhibits a relatively low resistance.
At least one type of phase change memory device, called PRAM, uses the amorphous state to represent a logical ‘1’ and the crystalline state to represent a logical ‘0’. In a PRAM device, the crystalline state is referred to as a “SET state” and the amorphous state is referred to as a “RESET state”. Accordingly, a memory cell in a PRAM stores a logical ‘0’ by setting a phase change material in the memory cell to the crystalline state, and the memory cell stores a logical ‘1’ by setting the phase change material to the amorphous state.
The phase change material in a PRAM is converted to the amorphous state by heating the material to a first temperature above a predetermined melting temperature and then quickly cooling the material. The phase change material is converted to the crystalline state by heating the material at a second temperature lower than the melting temperature but above a crystallizing temperature for a sustained period of time. Accordingly, data is programmed to memory cells in a PRAM by converting the phase change material in memory cells of the PRAM between the amorphous and crystalline states using heating and cooling as described above.
The phase change material in a PRAM typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), (i.e. a “GST” compound). The GST compound is well suited for a PRAM because it can quickly transition between the amorphous and crystalline states by heating and cooling. In addition to, or as an alternative for the GST compound, a variety of other compounds can be used in the phase change material. Examples of the other compounds include, but are not limited to, 2-element compounds such as GaSb, InSb, InSe, Sb2Te3, and GeTe, 3-element compounds such as GeSbTe, GaSeTe, InSbTe, SnSb2Te4, and InSbGe, or 4-element compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe), and Te81 Ge15Sb2S2.
The memory cells in a PRAM are called “phase change memory cells”. A phase change memory cell typically comprises a top electrode, a phase change material layer, a bottom electrode contact, a bottom electrode, and an access transistor. A READ operation is performed on the phase change memory cell by measuring the resistance of the phase change material layer, and a PROGRAM operation is performed on the phase change memory cell by heating and cooling the phase change material layer as described above.
FIGS. 1A and 1B show circuit diagrams illustrating a conventional phase change memory cell with an MOS embodiment 10 and a conventional diode based embodiment 30. Referring to FIG. 1A, memory cell 10 includes a phase change resistance element 16 comprising a GST compound, and a N-type metal-oxide semiconductor (NMOS) transistor 18. The phase change resistance element 16 is connected between a Bit-line 12 and an NMOS transistor 18. The NMOS transistor 18 is connected between the phase change resistance element 16 and ground 22 (also called VSS). In addition, the NMOS transistor 18 has a gate connected to a Word-line 14. The NMOS transistor 18 is turned on in response to a voltage applied to the Word-line. When the NMOS transistor 18 is turned on, current flows from the Bit-line 12 through the phase change resistance element 16 and the NMOS transistor 18 to ground 22.
Referring to FIG. 1B, the memory cell 30 comprises a phase change resistance element 36 comprising a GST compound, connected to a Bit-line 32, and a diode 38 is connected between the phase change resistance element 36 and a Word-line 34. The phase change memory cell 30 is accessed by selecting the Word-line 34 and the Bit-line 32. In order for the phase change memory cell 30 to work properly, the Word-line 34 must have a voltage level lower than the Bit-line 32 by at least the built-in diode voltage of diode 38, so that current can flow through the phase change resistance element 36. To ensure that the Word-line 34 has a sufficiently lower voltage level than the Bit-line 32, the Word-line 34 is generally connected to ground when selected.
In FIGS. 1A and 1B, the phase change resistance elements 16 and 36 can alternatively be broadly referred to as “memory elements” and the NMOS transistor 18 and the diode 38 can alternatively be broadly referred to as “select elements”.
The operation of the phase change memory cells 10 and 30 is described below with reference to FIG. 2. In particular, FIG. 2 is a graph illustrating temperature characteristics of the phase change resistance elements 16 and 36 during PROGRAM operations of the memory cells 10 and 30. In FIG. 2, a curve 52 shows the temperature characteristics of the phase change resistance elements 16 and 36 during a transition to the amorphous state, and a curve 54 shows the temperature characteristics of the phase change resistance elements 16 and 36 during a transition to the crystalline state.
Referring to FIG. 2, during a transition to the amorphous state, a current is applied to the GST compound in phase change resistance elements 16 and 36 for a duration T1 56 to increase the temperature of the GST compound above a melting temperature Tm 58. After the duration T1 56, the temperature of the GST compound is rapidly decreased, or “quenched”, and the GST compound assumes the amorphous state. Conversely, in a transition to the crystalline state, a current is applied to the GST compound in the phase change resistance elements 16 and 36 for an interval T2 60 (where T2 is greater than T1) to increase the temperature of the GST compound above a crystallization temperature Tx 62. At T2, the GST compound is slowly cooled down below the crystallization temperature so that it assumes the crystalline state.
A phase change memory device typically comprises a plurality of phase change memory cells arranged in a memory cell array. Within the memory cell array, each of the memory cells is typically connected to a corresponding bit-line and a corresponding word-line. For example, the memory cell array may comprise bit-lines arranged in columns and word-lines arranged in rows, with a phase change memory cell located near each intersection between a column and a row.
Typically, a row of phase change memory cells connected to a particular word-line is selected by applying an appropriate voltage level to the particular word line. For example, to select a row of phase change memory cells similar to phase change memory cell 10 illustrated in FIG. 1A, a relatively high voltage level is applied to a corresponding word-line 14 to turn on the NMOS transistor 18. Alternatively, to select a row of phase change memory cells similar to the phase change memory cell 30 illustrated in FIG. 1B, a relatively low voltage level is applied to a corresponding word-line 34 so that current can flow through diode 38.
Unfortunately, where a PROGRAM current is simultaneously applied to the plurality of diode based memory cells connected with one word-line, a voltage level of the word-line may undesirably increase due to the parasitic resistance and parasitic capacitance of the word-line. As the voltage level of the word-line increases, the programming characteristics of the plurality of memory cells may deteriorate because the voltage across the memory element decreases resulting in less temperature rise in the memory element. In addition, if the voltage level of the word-line increases too much, the diode 38 shown in FIG. 1B can not sufficiently turn on.
One U.S. Pat. No. 7,463,511 granted to Choi et al. on Dec. 9, 2008 discloses one approach to minimizing the voltage level change on a sub-word-line, which is to use a sub-word-line driver on either end of the sub-word-line. In this approach, sub-word-line drivers are used on either end of a sub-word-line with parasitic resistance. Each memory cell sinks current from their respective write drivers, through column select transistors. The sunk current develops a voltage across the parasitic resistance and the resistance of the NMOS devices in the sub-word-line drivers respectively. This approach suffers from a common ground line and associated resistance used by the sub-word-line drivers.